Microprocessors, digital signal processors, digital imaging devices, and many other types of digital data processing devices rely on an attached high-speed memory system to hold data and/or processor instructions needed by the processing device. As these processing devices become faster and more powerful, the increased demands placed on them generally translate to a need for larger and faster attached memory systems.
FIG. 1 depicts a typical memory system configuration 20. A host processor 22 issues data store and retrieve requests to a memory controller 24 over a front-side bus FSB. Memory controller 24 acts as an intermediary for the exchange of data between processor 22 and memory units 26A, 26B, 26C, and 26D.
Typical memory systems have an address/command bus 28 and a separate data bus 30, each of which carries memory signals on a set of signal lines. Memory signals fall generally into one of several categories including clock and control signals, address signals, command signals, and data signals. Data signals carry the actual data that will be stored in, or retrieved from, a memory device, and pass across data bus 30. Address signals specify the location within a memory device where data is to be read from or written to. Command signals instruct a memory device as to what type of operation is to be performed, e.g., read, write, refresh, and possibly as to which of several access modes (such as a burst mode) should be used for a data transfer. Address/command bus 28 may have separate address lines and command lines, or addresses and commands may share a common set of lines and use temporal address/command separation. Clock and control signals synchronize the other signals passing between controller 24 and the memory devices. Four control signal lines are shown in FIG. 1—the chip select signal lines CSA, CSB, CSC, and CSD. When memory controller 24 places addresses and commands on bus 28, it asserts a chip select signal corresponding to the memory unit that it is targeting. The selected memory unit processes the command and performs the requested read or write command; the other units remain idle.
In the configuration shown in FIG. 1, data bus 30 is a multi-drop memory bus. In other words, bus 30 is arranged with a backbone of signal lines. A signal line stub, or “drop”, connects each of the memory devices to the backbone, e.g., drops 30A, 30B, 30C, and 30D. Electrically, each stub or drop is a potential source of noise on data bus 30, as signal reflections from stubs connected to idle memory units can reach the intended recipient of a data transfer out-of-phase with the original signaling, increasing the probability that erroneous data will be sensed at the receiver.
As data bus speeds increase—even as logical voltage swings decrease in some cases—to increase memory capabilities, reflected signals become increasingly problematic. FIG. 2 shows one memory system implementation 40 that addresses this problem. Memory units 46A and 46B connect with controller 42 conventionally using an address/command bus 28, a data bus 30, and chip select signal lines CSA and CSB. Two additional control signal lines, TEA and TEB, can be asserted respectively to memory units 46A and 46B.
Each device communicating on bi-directional data bus 30 has a receiver/driver circuit (R/DA and R/DB, respectively, for memory units 46A and 46B, R/DC for controller 42) coupled to its stub of the data bus. In addition, each device has a termination circuit (TCA, TCB, TCC) coupled to its stub of the data bus. When enabled, each termination circuit absorbs signals propagating down its respective stub, thus diminishing the amount of energy reflected on that stub.
Termination control logic 44, residing within memory controller 42, controls the state of each termination circuit. For instance, when controller 42 is writing data to memory unit 46A, it asserts both TEA and TEB to enable termination circuits TCA and TCB. When controller 42 is reading data from memory unit 46A, it deasserts TEA and asserts TEB, and internally asserts TEC. Similar but reversed termination signaling occurs when memory unit 46B is the target device. This is but one example—TEA and TEB could be operated according to various other termination rules.